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PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
Document Title
512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Add 30pF capacitive in test load. 2.3. Relax DC characteristics. Item Previous ICC 10ns 170mA 12ns 160mA 15ns 150mA ISB f=max. 40mA ISB1 f=0 10 / 1mA IDR VDR=3.0V 0.9mA Draft Data Jan. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary
Rev. 2.0
Feb.11th.1998
Final
Current 205mA 200mA 195mA 50mA 10 / 1.2mA 1.0mA Jun.27th 1998 Final
Rev. 2.1
Change operating current at Industrial Temperature range. Previous spec. Changed spec. Items (10/12/15ns part) (10/12/15ns part) Icc 205/200/195mA 230/225/220mA Add 44 pins plastic TSOP(II) forward Package.
Rev. 2.2
May. 4th 1999
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
* Fast Access Time 10,12,15ns(Max.) * Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 10mA(Max.) 1.2mA(Max.)- L-Ver. Operating K6R4008V1B-10 : 205mA(Max.) K6R4008V1B-12 : 200mA(Max.) K6R4008V1B-15 : 195mA(Max.) * Single 3.3 0.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention ; L-Ver. only * Center Power/Ground Pin Configuration * Standard Pin Configuration K6R4008V1B-J : 36-SOJ-400 K6R4008V1B-T: 36-TSOP2-400F K6R4008V1B-U: 44-TSOP2-400AF
CMOS SRAM
GENERAL DESCRIPTION
The K6R4008V1B is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The K6R4008V1B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4008V1B is packaged in a 400 mil 36-pin plastic SOJ or TSOP(II) forward or 44-pin plastic TSOP(II) forward.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0 A1 A3 A4 A5 A6 A7 A8 I/O1~I/O8 A2
ORDERING INFORMATION
K6R4008V1B-C10/C12/C15 Commercial Temp. Industrial Temp. K6R4008V1B-I10/I12/I15
Pre-Charge Circuit
Row Select
Memory Array 512 Rows 1024x8 Columns
Data Cont. CLK Gen.
I/O Circuit Column Select
PIN FUNCTION
Pin Name A0 - A18 WE Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground No Connection
A10 A12 A14 A16 A18 A9 A11 A13 A15 A17
CS OE
CS WE OE
I/O1 ~ I/O8 VCC VSS N.C
-2-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
PIN CONFIGURATION(Top View)
CMOS SRAM
N.C A0 A1 A2 A3 A4 CS I/O1 I/O2 Vcc Vss 1 2 3 4 5 6 7 8 9 10 36 N.C 35 A18 34 A17 33 A16 32 A15 31 OE 30 I/O8 N.C A0 A1 A2 A3 A4 CS I/O1
1 2 3 4 5 6 7 8 9
44 N.C 43 N.C 42 N.C 41 40 39 38 37 A18 A17 A16 A15 OE
36 I/O8 35 I/O7
36-SOJ/ TSOP2
29 I/O7 28 Vss 27 Vcc 26 I/O6 25 I/O5 24 A14 23 A13 22 A12 21 A11 20 A10 19 N.C
I/O2 10 Vcc 11 Vss 12 I/O3 13 I/O4 14 WE A5 A6 A7 A8 A9 15 16 17 18 19 20
44-TSOP2
34 Vss 33 Vcc 32 I/O6 31 I/O5 30 29 28 27 26 A14 A13 A12 A11 A10
I/O3 11 I/O4 12 WE A5 A6 A7 A8 A9 13 14 15 16 17 18
25 N.C 24 N.C 23 N.C
N.C 21 N.C 22
PIN FUNCTION
Pin Name A0 - A18 WE CS OE I/O1 ~ I/O8 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3** Typ 3.3 0 Max 3.6 0 VCC+0.3*** 0.8 Unit V V V V
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=3.30.3V, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 10ns 12ns 15ns Standby Current ISB ISB1 Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN 0.2V IOL=8mA IOH=-4mA Normal L-Ver. Test Conditions Min -2 -2 2.4 Max 2 2 205 200 195 50 10 1.2 0.4 V V mA mA Unit A A mA
Output Low Voltage Level Output High Voltage Level
VOL VOH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 7
Unit pF pF
-4-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
AC CHARACTERISTICS(TA=0 to 70C, VCC=3.30.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
* The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value 0V to 3V 3ns 1.5V See below
Output Loads(A)
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V RL = 50
DOUT
VL = 1.5V
ZO = 50 30pF*
319 DOUT 353 5pF*
* Capacitive Load consists of all components of the test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R4008V1B-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 5 15 K6R4008V1B-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 K6R4008V1B-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
-5-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
WRITE CYCLE*
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R4008V1B-10 Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 K6R4008V1B-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 K6R4008V1B-15 Min 15 10 0 10 10 15 0 0 7 0 3 Max 7 Unit ns ns ns ns ns ns ns ns ns ns ns
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address tOH Data Out Previous Valid Data tAA Valid Data
(Address Controlled, CS=OE=VIL, WE=VIH)
tRC
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) Valid Data tPU 50% tPD 50% tOH tOHZ tHZ(3,4,5)
CS
NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-6-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW
(10) (9)
tWR(5)
tWP1(2)
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
High-Z(8)
-7-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS H L L L
* X means Dont Care.
WE X H H L
OE X* H L X
Mode Not Select Output Disable Read Write
I/O Pin High-Z High-Z DOUT DIN
Supply Current ISB, ISB1 ICC ICC ICC
DATA RETENTION CHARACTERISTICS*(TA=0 to 70C)
Parameter VCC for Data Retention Data Retention Current Symbol VDR IDR Test Condition CS VCC - 0.2V VCC=3.0V, CSVCC - 0.2V VINVCC - 0.2V or VIN 0.2V VCC = 2.0V, CSVCC - 0.2V VINVCC - 0.2V or VIN0.2V Data Retention Set-Up Time Recovery Time tSDR tRDR See Data Retention Wave form(below) Min. 2.0 Typ. Max. 3.6 1.0 Unit V mA
-
-
0.7
mA ns ms
0 5
-
-
* The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0V tSDR Data Retention Mode
tRDR
VIH VDR CSVCC - 0.2V
CS GND
-8-
Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
PACKAGE DIMENSIONS
36-SOJ-400
#36 #19
CMOS SRAM
Units:millimeters/Inches
11.18 0.12 0.440 0.005
10.16 0.400
9.40 0.25 0.370 0.010
0.20 #1 23.90 MAX 0.941 23.50 0.12 0.925 0.005 1.19 ) 0.047 1.27 ( ) 0.050 ( 0.43 ( 0.95 ) 0.0375
+0.10 -0.05
+0.10 -0.05
#18 0.69 MIN 0.027
0.008 +0.004 -0.002
3.76 MAX 0.148
0.10 MAX 0.004
0.017 +0.004 -0.002
1.27 0.050
0.71 +0.10 -0.05 0.028 +0.004 -0.002
36-TSOP2-400F
0~8
#36
#19
0.45 ~0.75 0.018 ~ 0.030
10.16 0.400
11.76 0.20 0.463 0.008
#1 18.81 0.741 MAX 18.41 0.10 0.725 0.004
#18 0.15
+0.10 -0.05
(0.50) (0.020) 0.006 +0.004 -0.002
1.00 0.10 0.039 0.004 (0.705) (0.028) 0.40 0.10 0.016 0.004 1.00 0.039 TYP 0.05 0.002MIN
1.20 0.047 MAX
0.10 MAX 0.075 MAX
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Rev 2.2 May 1999
PRELIMINARY
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
44-TSOP2-400AF
0.25 ( ) 0.010 #44 #23 0.45 ~0.75 0.018 ~ 0.030
CMOS SRAM
0~8
11.76 0.20 0.463 0.008
10.16 0.400
#1 18.81 MAX. 0.741 18.41 0.10 0.725 0.004
#22
0 + 0.1 0.05 0.15 - .00 4 0 + 02 .006 - 0.0
( 0.50 ) 0.020
0
1.00 0.10 0.039 0.004 ( 0.805 ) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 0.05 MIN. 0.002
1.20 MAX. 0.047
0.10 0.004 MAX
- 10
Rev 2.2 May 1999

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